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Researchers have devised a “back-end memory transistor” that combines a processing unit (the transistor) with a storage unit.(Image credit: Christine Daniloff, MIT; iStock)ShareShare by:
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MIT engineers suggest that arranging circuit parts one atop the other may present a solution for designing more power-saving artificial intelligence (AI) chips. The logic and memory segments, which conduct calculations and retain information respectively, can exchange information more conveniently through direct contact, rather than when physically separated.
The team originated a “memory transistor,” encompassing a logic component capable of carrying out operations (the transistor) and a storage segment. This diminutive device possesses relatively few electrical flaws, indicating enhanced speed and reduced energy consumption, according to findings shared in a pair of studies presented on December 9 and 10 during the International Electron Devices Meeting held in San Francisco.
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A single interaction with ChatGPT can produce sufficient warmth to necessitate a water bottle’s worth of cooling. However, the majority of energy linked with AI is expended conveying data between components rather than conducting computations. Even a modest energy conservation at the chip level could yield significant results, the scientists believe.
“We must lessen the degree of energy utilized for AI and other data-focused computation moving forward as it’s simply untenable,” stated Yanjie Shao, the study’s lead author and a postdoctoral researcher at MIT, via a press release. “To continue advancing, we’ll require novel technology like this integration platform.”
Stacking conserves energy — yet poses difficulties
Modern chips incorporate logic circuits fabricated from transistors, which act as on/off mechanisms governing current flow. These transistors merge to denote binary 1s and 0s, enabling information processing by chips. Additionally, they feature memory circuits, containing transistors along with other substances capable of data storage.
Logic and storage circuits are generally maintained separately, necessitating data transfer through wires and interconnections, resulting in energy wastage. Although arranging the active parts vertically may appear to be an intuitive solution, the challenge lies in executing it without inducing damage. For instance, deposition, the regulated creation of extremely thin layers forming these components, must occur at lower temperatures because certain transistors cannot endure elevated heat.
To resolve this issue, the researchers constructed their logic transistor employing an active channel layer (the zone facilitating electricity flow) composed of indium oxide. Significantly, the substance can be placed in a two-nanometer layer at approximately 302 degrees Fahrenheit (150 degrees Celsius). This temperature is adequately low to avoid impacting other transistors.
Beyond the indium oxide transistor, the scientists vertically assembled a memory element — a 10-nanometer layer of ferroelectric hafnium-zirconium-oxide — empowering the device to both retain and manipulate data. The subsequent memory transistor can activate or deactivate in a mere 10 nanoseconds, running at less than 1.8 volts. The switching velocities of typical ferroelectric memory transistors generally rank significantly lower and demand voltages ranging from 3 to 4V.
The memory transistor attains even greater efficiency through construction on the chip’s “back-end,” housing the wires and metal connections that link the front-end’s active components. According to Shao, this process significantly enhances the chip’s integration density.
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For the purposes of the two studies, the memory transistor existed solely on a chip-like framework instead of a functional circuit. The team anticipates refining the transistor’s capabilities, enabling its initial integration into a distinct circuit, followed by incorporation into more extensive electronic systems.
“Presently, we are capable of erecting a platform of adaptable electronics on a chip’s back end, facilitating elevated energy efficiency and diverse functionalities in extremely compact devices,” Shao stated. “We possess a favorable device architecture and material to proceed with; however, continued innovation remains vital for unveiling the ultimate performance capabilities.”
Fiona Jackson
Fiona Jackson acts as an independent writer and editor, with a primary focus on science and technology. She has functioned as a news writer within the science division at MailOnline, and has also reported on technology news for TechRepublic, eWEEK, and TechHQ.
Fiona gained vital experience penning human interest narratives for global news sources at the SWNS press agency. She possesses a Chemistry Master’s degree, an NCTJ Diploma, and shares her residence in Bristol, UK, with a cocker spaniel called Sully.
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